As integrated circuits become increasingly complex, the need for increased packaging density and reduced device parasitics increases. Conventional nonelevated source/drain (SD) regions have been widely used for sub-0.25 μm CMOS technology, but problems associated with heavily doping the SD regions while simultaneously maintaining shallow extension junctions at the channel regions have led to the increased implementation of epitaxial RSD structures. Epitaxial RSD structures allow for ultra shallow junctions and reduce SD resistance in CMOS devices. However, a side effect of the epitaxial RSD structures is an increased parasitic capacitance between the gate and the RSD regions resulting in decreased transistor radio-frequency (RF) performance in terms of speed and noise. The adverse impact of parasitic capacitance on device performance increases greatly as CMOS technology continues to be downscaled to 22 nm and smaller. Accordingly, it may be desirable to overcome the deficiencies and limitations described hereinabove.